By Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Advanced try out tools for SRAMs: powerful suggestions for Dynamic Fault Detection in Nanoscaled Technologies
Modern electronics is dependent upon nanoscaled applied sciences that current new demanding situations by way of checking out and prognosis. thoughts are rather at risk of defects seeing that they make the most the know-how limits to get the top density. This e-book is a useful consultant to the trying out and prognosis of the most recent iteration of SRAM, essentially the most normal kind of stories. Classical equipment for checking out reminiscence are designed to address the so-called "static faults", yet those try out suggestions aren't adequate for faults which are rising within the most modern Very Deep Sub-Micron (VDSM) applied sciences. those new faults, often called "dynamic faults", will not be coated through classical algorithms and require the devoted try and prognosis strategies offered during this book.
- First publication to provide entire, state of the art insurance of dynamic fault trying out for SRAM memories;
- Presents content material utilizing a "bottom-up" strategy, from the examine of explanations of malfunctions as much as the iteration of shrewdpermanent attempt recommendations;
- Includes case reports masking all reminiscence elements (core-cells, tackle decoders, write drivers, feel amplifiers, etc.);
- Proposes an exhaustive research of resistive-open defects in every one reminiscence part and the ensuing dynamic fault modeling.
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Additional resources for Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies
2005c, Dilillo et al. 2008). For this purpose, the results of electrical simulations are reported considering an 8 K × 32 memory organized as an array of 512 word lines × 512 bit lines. The resistance values are chosen in a range between few ohms up to several Mohms to produce a complete view on the studied phenomena. 9 V) Simulations performed in the ‘active mode’ (normal functional mode) In Fig. 20, the graph represents for each technology the minimal value of resistance that leads to malfunctions.
The modification, which makes March C- able to detect dRDFs, consists in the use of the particular address sequence word line after word line. 4), this modification does not change the capability of March C- to detect the former targeted faults. The efficiency of the modified March C- can be evaluated considering a given SRAM architecture (Dilillo et al. 2005b). Let us assume that the defective core-cell is Ci, 0, the first one of row i. Element M2 operates a w0 on Ci, 0 , and just after the couple of (r1,w0) operations on the following 511 core-cells of the same row i, resulting in 2·511 = 1022 RESs on the defective core-cell.
Defect Df3 is in the refreshment loop and may lead to a dynamic Read Destructive Fault (dRDF). Defect Df4: This defect is placed in the pull-up of INV1 and may induce static and dynamic faults (Zarrineh et al. 2000, Dilillo et al. 2005a). For large resistance values of Df4, static RDFs and DRDFs occur as for defect Df2. Very large values of resistance lead to spontaneous data loss of the core-cell: Data Retention Faults (DRFs). For low values of resistance, multiple consecutive read operations may lead to core-cell content swap (dynamic RDFs).